6809/6309 Mnemonic Lookup

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Instruction: Lookup

Mnemonic: Lookup

* = 6309		Immediate			Direct			Indexed			Extended			Inherent			Relative			Register			Memory
*	Mnemonic	Opcode	Cycles	Length	Opcode	Cycles	Length	Opcode	Cycles	Length	Opcode	Cycles	Length	Opcode	Cycles	Length	Opcode	Cycles	Length	Opcode	Cycles	Length	Opcode	Cycles	Length
	ORCC	1A	3/2	2

Description:

Logically OR the CC Register with an Immediate Value [CC' <- CC OR IMM8]

Documenation

If an interrupt mask bit is 1, the corresponding interrupt is disabled. The following are macros to be used for setting and clearing the CC register flags.

; CC register flags
FIRQ            equ     %01000000
IRQ             equ     %00010000
OVERFLOW        equ     %00000010
CARRY           equ     %00000001

;
; Carry
;
; Clear carry flag
clc             macro
                andcc   #~CARRY
                endm
; Set carry flag
sec             macro
                orcc    #CARRY
                endm
;
; firq & irq
; If an interrupt mask bit is 1, the corresponding interrupt is disabled.
;
; Clear Fast Interrupt Mask
clf             macro
                andcc   #~FIRQ
                endm
; Clear Regular Interrupt Mask
cli             macro
                andcc   #~IRQ
                endm
; Clear Regular and Fast Interrupt Masks
clif            macro
                andcc   #~(FIRQ|IRQ)    ; ANDCC #%1010111
                endm
; Set Fast Interrupt Mask
sef             macro
                orcc    #FIRQ
                endm
; Set Interrupt Mask
sei             macro
                orcc    #IRQ
                endm
; SEIF - Set Regular and Fast Interrupt Masks
seif            macro
                orcc    #FIRQ|IRQ
                endm

;
; Overflow Flag
;
; Clear Overflow Flag
clv             macro
                andcc   #~OVERFLOW
                endm
; Set Overflow Flag
sev             macro
                orcc    #OVERFLOW
                endm

Example

 orcc   #FIRQ|IRQ        ; disable interrupts 
 andcc   #~(IRQ|FIRQ)    ; enable  interrupts

 orcc   #$50             ; disable interrupts
 andcc  #$AF             ; enable  interrupts