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You can also lookup mnemonics like LDX,LDY in the mnemonic field.
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Show All | Registers | Addressing Modes | Post Bytes | Acknowledgments | Sock's GIME Reference | Sock's CPU Cycle Data Charts
Not case sensitive.
* = 6309 | Immediate | Direct | Indexed | Extended | Inherent | Relative | Register | Memory | |||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
* | Mnemonic | Opcode | Cycles | Length | Opcode | Cycles | Length | Opcode | Cycles | Length | Opcode | Cycles | Length | Opcode | Cycles | Length | Opcode | Cycles | Length | Opcode | Cycles | Length | Opcode | Cycles | Length |
* | TIM | 0B | 6 | 3 | 6B | 7+ | 3+ | 7B | 7 | 4 |
E | F | H | I | N | Z | V | C |
- | - | - | - | X | X | 0 | - |
Bit Test Immediate Value with Memory Byte [TEMP ← (M) AND IMM8]
DocumenationThe TIM instruction logically ANDs the contents of a byte in memory with an 8-bit immediate value. The resulting value is tested and then discarded. The Condition Codes are updated to reflect the results of the test as follows:
TIM can be used as a space-saving optimization for a pair of equivalent 6809 instructions, and to perform a bit test without having to utilize a register. However, it is slower than the 6809 equivalent:
6809: (4 instruction bytes; 7 cycles):
LDA #$3F
BITA 4,U
6309: (3 instruction bytes; 8 cycles):
TIM #$3F;4,U
Note that the assembler syntax used for the TIM operand is non-typical. Some assemblers may require a comma (,) rather than a semicolon (;) between the immediate operand and the address operand.